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Integrated Circuits Inc. AP8842
APLUS
MAKE YOUR PRODUCTION A-PLUS
VOICE OTP IC AP8842 - 42 VOICE OTP
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail:
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
sales@aplusinc.com.tw
Technology E-mail:
service@aplusinc.com.tw
Ver 1.3
1
Integrated Circuits Inc. AP8842 42 sec VOICE OTP
Features 42 Sec Voice Length at 6 KHz Combination of voice building blocks extends the duration of playback Voice data re-use saves memory space Maximum 30 voice groups 8 trigger pins, S1 to S8 for the 8 voice groups ( group1 ~ 8 ) SBT for sequential playblack the rest of voice groups & for CPU mode trigger S1 to S5 in CPU trigger mode to trigger all 30 voice groups Holdable, Unholdable, Edge, Level triggering option Debounce time : 22ms for both Key and CPU mode @ 6K sampling rate IRP interrupt pin for master reset General Description AP8842 is a high quality voice synthesizer capable of varying playback duration. A proprietary ADPCM algorithm is used. The audio message is stored in a 1M bits on-chip EPROM which can store up to 42 seconds of voice data at 6 KHz sample rate. The AP8842 eliminates the need of complicated circuitry in voice playback but still achieves high voice quality for different kind of sounds. Combinations in sections achieve longer playback duration. A pair of PWM output pins, VOUT1 and VOUT2 provides direct drive to buzzer or speaker. A current output pin, COUT, enables the device to drive a speaker through a low cost NPN transistor. No complex filtering or amplifier circuit is needed. An automatic ramp-down function eliminates undesired noise at the end of playback. 3 programmable Outputs for STP stop pulse, BUSY and LEDs Built-in oscillator with a single external resistor to determine the sampling rate Built-in D/A converter, EPROM ADPCM data compression provides high sound quality Optional POP noise elimination function COUT pin drives speaker with a transistor VOUT1 and VOUT2 drives buzzer or speaker directly Auto-power down 2.7V - 3.8V single power supply operation Low standby current (<5uA at 3V) Development Tools Support
Ver 1.3
2
Integrated Circuits Inc. AP8842
Group of sections The voice memory of the AP8842 is subdivided into 254 memory blocks. Any combination of playback of these memory blocks will form an individual voice group. A maximum of 30 groups are available with triggering S1 to S5 pins together with the SBT pin in CPU trigger mode. In Key trigger mode, S1 to S8 pins are used to trigger the beginning 8 voice groups. The rest of the voice groups can be triggered one by one sequentially with the SBT pin. Group Configuration Data within each group are combinations of different fixed memory blocks of up to 254 blocks. They are the fundamental building blocks for arranging playback without limiting sequencing. This provides flexibility and allows data to be re-used, beneficial for applications with many repeated sounds or words. An example of group configuration is illustrated below:
Group no. Group 1 Group 2 Group 3 Group 4
Section entry Block 1 + Block 2 + Block 3 ....... + Block 109 Block 3 + Block 2 Block 10 + Block 11 + Block 12 Block 10 + Block 10 + Block 5
The entries of blocks for each group is truly random and without limitation. However, there is a limit in the total number of entries for 30 voice groups, which is 896 entries in AP8842. It is acceptable to allocate all entries into only one group or distribute out to other groups. It depends on how many groups of messages are required. Programmable Options Each groups in AP8842 can have independent options. They are: Edge or Level trigger Unholdable or Holdable trigger Re-triggerable or non-retriggerable Outputs are programmable to LED1, LED2, BUSY and STOP pulse Options that affect all voice groups are called whole chip options. They are: Key trigger mode or CPU trigger mode Ramp enable (for Cout drive) or Ramp disable (for Vout drive)
Ver 1.3
3
Integrated Circuits Inc. AP8842
Output Selections There are three independent output pins OUT1, OUT2 and OUT3, available for four combinations of LED1, LED2, STOP and BUSY signals for each voice group. Options 1. 2. 3. 4. OUT1 LED2 STOP LED1 LED1 OUT2 LED1 LED1 BUSY BUSY OUT3 BUSY LED2 STOP /BUSY
LED1 and LED2 are complemented outputs flashing at a fix interval. STOP pulse gives a long enough positive pulse at the end of the playback for each group with option to enable or disable it. BUSY is active high during voice playback. Software Support All those Options and Output selections can be set with a dedicated OTP compiler and programmer software supplied by APLUS. Key trigger mode and CPU trigger mode In Key trigger mode, S1 to S8 will trigger eight voice groups. The rest of the voice groups can only be triggered by SBT sequential trigger pin. In CPU trigger mode, binary data is input through S5 to S1. A high pulse is input to SBT pin with pulse width equal to or longer than the debounce time to strobe the data to initial the playblack. Data patterns "11110" and "11111" are reserved and not allowed.
Group-n S5 Group1 0 Group2 0 Group3 0 Group4 0 Group5 0 Group6 0 Group7 0 Group8 0
S4 0 0 0 0 0 0 0 0
S3 0 0 0 0 1 1 1 1
S2 0 0 1 1 0 0 1 1
S1 0 1 0 1 0 1 0 1
Group-n S5 Group9 0 Group10 0 Group11 0 Group12 0 Group13 0 Group14 0 Group15 0 Group16 0
S4 1 1 1 1 1 1 1 1
S3 0 0 0 0 1 1 1 1
S2 0 0 1 1 0 0 1 1
S1 0 1 0 1 0 1 0 1
Ver 1.3
4
Integrated Circuits Inc. AP8842
Group-n S5 Group17 1 Group18 1 Group19 1 Group20 1 Group21 1 Group22 1 Group23 1 Group24 1
S4 0 0 0 0 0 0 0 0
S3 0 0 0 0 1 1 1 1
S2 0 0 1 1 0 0 1 1
S1 0 1 0 1 0 1 0 1
Group-n S5 Group25 1 Group26 1 Group27 1 Group28 1 Group29 1 Group30 1 Reserve 1 Reserve 1
S4 1 1 1 1 1 1 1 1
S3 0 0 0 0 1 1 1 1
S2 0 0 1 1 0 0 1 1
S1 0 1 0 1 0 1 0 1
Block Diagram
Absolute Maximum Rating
Symbol VDD - VSS VIN VOUT T (Operating) T (Storage) Rating -0.5 ~ +4.5 VSS - 0.3Ver 1.3
5
Integrated Circuits Inc. AP8842
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name S8 OUT1 VOUT1 VOUT2 VSS OUT2 OUT3 COUT OSC S5 S6 VPP S1 S2 VDD S3 S4 SBT IRP S7 I/O/P I O O O P O O O I I I P I I P I I I I I Function Trigger switch 8, internal pull low, active high Programmable output 1 PWM audio signal output 1 for buzzer & speaker PWM audio signal output 2 for buzzer & speaker Power ground Programmable output 2 Programmable output 3 Current output from internal DAC for speaker playback Oscillator resistor pin to control sampling frequency Trigger switch 5 / CPU Addr.5 ( MSB ), Trigger switch 6, internal pull low, active high Program power, must connect to VDD when playback Trigger switch 1 / CPU Addr.1 ( LSB ), internal pull low, active high Trigger switch 2 / CPU Addr.2, internal pull low, active high Positive power supply internal pull low, active high internal pull low, active high Key Sequential/CPU trigger, internal pull low, active high Interrupt to stop playback, internal pull low, active high Trigger switch 7, internal pull low, active high
Note1: The following pins are used to program data into the memory: 5 - 7 and 9 - 20. Note2: Vpp and Vcc MUST be connected to positive power supply during normal playback. However, they MUST be separated during data programming. Ver 1.3 6
Integrated Circuits Inc. AP8842
DC Characteristics
Symbol VDD ISB IOP VIH VIL IOL IOH ICO IOH IOL F/F
Parameter Operating Voltage Standby current Operating current "H" Input Voltage "L" Input Voltage VOUT low O/P Current VOUT high O/P Current COUT O/P Current O/P high Current O/P low Current Frequency Stability
Min. 2.7
Typ. 3.0 1
Max. 3.8 5 15
Unit V
A
Condition
VDD=3.0V, I/O open VDD=3.0V, I/O open VDD=3.0V VDD=3.0V VDD=3.0V, Vout=0.3V VDD=3.0V, Vout=2.5V VDD=3.0V,VCOUT=1.0V VDD=3.0V, VOH=2.5V VDD=3.0V, VOL=0.3V Fosc(2.7V) - Fosc(3.4V) Fosc(3V)
mA V V mA mA mA mA mA
2.5 -0.3
3.0 0 120 -65 -3 -8 8
3.5 0.5
-5
5
%
Ver 1.3
7
Integrated Circuits Inc. AP8842
AC Characteristics
1. INPUT SETUP AND HOLD TIME : KEY Trigger Mode : S1 to S8 hold time, th (min.) = 22ms @ 6K Hz sampling
CPU Trigger Mode : SBT setup time ts (min.) = 1us, and S1 to S5 hold time th (min.) = 22ms @ 6K Hz sampling
Note: Input hold time th is inverse proportional to the sampling frequency. 2. OUTPUTS DELAY TIME : STOP : Delay time td (max.) = 1us, plus width tw (min.) = 64ms @ 6K Hz sampling
Note: The pulse width tw is inverse proportional to the sampling frequency. BUSY : Delay time td (max.) = 1us, hold time th (max.) = 1us @ 6K Hz sampling
Note: The BUSY delay time td and hold time th is fixed and independent of sampling frequency. LED flash at fixed 2Hz @ 6K Hz sampling
Ver 1.3
8
Integrated Circuits Inc. AP8842
Timing Diagrams
1. Level, Unholdable, Non-retriggerable a. Trigger is shorter than a Group output b. Trigger is longer than a Group output
2. Level Holdable a. Trigger is shorter than a Group output
b. Trigger is longer than a Group output
3. Single Button Trigger(SBT), Sequential a. Level Unholdable
b. Level Holdable
where N is up to 30.
Ver 1.3
9
Integrated Circuits Inc. AP8842
4. Edge, Unholdable, Non-retriggerable a. Trigger is shorter than a Group output b. Trigger is longer than a Group output
5. Edge Holdable a. Trigger is shorter than a Group output b. Trigger is longer than a Group output
6. Single Button Trigger(SBT), Sequential a. Edge Unholdable
b. Edge Holdable
where N is up to 30.
Ver 1.3
10
Integrated Circuits Inc. AP8842
Application Circuits
1. Typical Application
Fig. 1a COUT with transistor
Fig. 1b VOUT direct drive
Ver 1.3
11
Integrated Circuits Inc. AP8842
2. CPU Mode control
Fig. 2
Bonding Pad Locations
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name
S8 OUT1 VOUT1 VOUT2 VSS OUT2 OUT3 COUT OSC S5 S6 VPP S1 S2 VDD S3 S4 SBT IRP S7
X
883 1024 1247 1625 1864 1876 1736 1598 1182 907 766 614 471 336 159 180 319 459 600 740
Y
180 180 180 180 180 2697 2697 2697 2697 2697 2697 2697 2697 2697 2697 180 180 180 180 180
Note:Substrate must be connected to VSS Pad size = 90um x 90um
Ver 1.3
12
Integrated Circuits Inc. AP8842
Ver 1.3
13
Integrated Circuits Inc. AP8842
Package : DIP - 20 pin - 300 mil
Ver 1.3
14

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